IC design process

The mixed-mode Asic design team will typically consist of Project Manager plus a number of analog design engineers, one or more digital design engineers and one or more layout engineers. This team is supported by the system architect and a test engineer. 

The IC design process starts by writing up of the Asic Implementation spec based on the customers Asic requirement spec. The Asic implementation spec is typically written by the Asic Project Manager assisted by the system Architect.  In order to define the right block specification the system architect may build a high level simulation model of the Asic to see if the right block level specs are assigned. Also in parallel some critical design blocks may be tested on circuit simulation in order to see if the specs are feasible.

Once the Asic implementation spec approved, the design can start. In the top down approach the analog design engineers will start with the design of the analog blocks and do circuit simulations to meet the analog block level specifications.  In parallel the digital design team will start the detailed implementation of the digital part, first on a functional level, afterwards on a level that is optimized for synthesis on the target digital library of the chosen technology. When the digital part is debugged  this version can be used to deliver an FPGA netlist in order to be used in the Asic-like Breadboard. In case of errors some iterations may be required.

Gradually when the analog circuit models become available, the bottom-up process can start whereby the architectural models are replaced by the circuit models and a mixed-mode simulation is done.

Whenever the circuit design of an analog block is finished, the layout of that block may start. The layout of that cell should keep into account the floorplan of the asic that should be made from the start of the project, taking into account pin order preference of the customer combined the package/leadframe restrictions. The digital part that is routed automatically and is typically one of the latest tasks in the process of layout.

Based on the results of the Asic-like breadboard and based on the outcome of different design review meetings the customer will sign of the Asic. Then the layout is ready to be send to mask making.


Package Specification

Chip Assembly Specification


When using a standard package,  only a reference to this package type has to be given.
However, when a standard package does not exist, a dedicated spec has to be made up, to define the new package. 
There are a huge number of package types used in the semiconductor industry, but lets here consider the overmoulding in a plastic package.

The two main components of such a  package are the leadframe, and the plastic overmould.

If only an adjustment of the leadframe needs to be done, then the package spec is not too complicated.   Such an adjustment for instance would be needed to adapt the die peddle size to the chip size.
Other modifications could be driven by material choice, leadframe thickness, …

If the plastic mold has to be adjusted, then the  implications are much more profound. Such a change of mold can be necessary for size restriction, thermal considerations, special form factor, use of cavity molding, ..

The package specification needs to contain of elements required by the package development subcontractor to design successfully the mold tool.



Test system Development

The development of a TestSystem starts with understanding the understanding of the product and it's blocks. When applyng all potential failure mechanism (nduces by the manufacturing process), then it becoimes clear what process defects will cause. Many times , the DFMEA will support the understanding of the expected failure rates.

Test Specification

Based on the list of potential defects, a list of tests can be drawn. (see Test Specification for more details)

Test System

Once, it's known what needs to be tested, the question come HOW to test the desired behavior. This will lead to a testsystem containing :

  • a testsystem with the desired testcapability
  • a test handler able to hanlde the packaged parts to get them electrical connected to test.. Many times, the test handler must be able to apply physical parameters as Temperature, pressure, light, vibration, ...
  • interface boards between tester and handler
  • a wafer prober to handle wafers to get the dies electrical connected for test. Also here temperature might be desired.
  • probecards to interface between tester and dies.

Design for Test Requirements

Once the test spec is known and the testsystem is selected, then it's clear what testtime (cost) will be reached and what coverage is feasible (depends on the device test infrastructure and the tester capability. Out of this, DFT requirements might be derived what needs to be breought back to the Product specification.

ICR will support

  • assuring the testspec meets the desired fault coverage
  • verifying if the test system can cover the test specification as proposed
  • assuring the DFT needs are addressed